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view tests/equiv.ur @ 2234:2f7ed04332a0

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Progress on LRU cache but still more known bugs to fix.
author Ziv Scully <ziv@mit.edu>
date Sun, 28 Jun 2015 12:46:51 -0700
parents 71bafe66dbe1
children
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type t1 = {A : int, B : float}
type t2 = {B : float, A : int}
val e1 : t1 -> t2 = fn x => x