view caching-tests/test.urs @ 2290:ab6ca12debeb

Add small benchmark (WIP).
author ziv@mit.edu
date Sun, 15 Nov 2015 18:10:24 -0500
parents c05f9a5e0f0f
children f8903af753ff
line wrap: on
line source
val cache : int -> transaction page
val cacheR : {Id : int, FooBar : int} -> transaction page
(* val cache2 : int -> int -> transaction page *)
val flush : int -> transaction page
val flash : int -> transaction page
val floosh : int -> transaction page
(* val flush17 : transaction page *)